New Contributor
Super ContributorCan you show the code that works vs. the code that doesn't? There's not much you can do if Quartus doesn't support localparam in the port list.
New ContributorHello,
Thank you for the reply.
I get an error during Analysis and Synthesis with Quartus if I do:
module my_module #(
paramater TEST0 = 8,
localparam TEST1 = 16
)(
input [TEST1:0] my_input
);
...
endmodule
There error reads:
Error (10170): Verilog HDL syntax error at my_module.sv(5) near text: "localparam"; expecting an identifier ("localparam" is a reserved keyword ). Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Thank you very much for any help you can provide!
Super ContributorHi @escottp
I think there is a limitation in the System Verilog language in Quartus lite.
The code is able to compile in Quartus Pro version.
Best Regards,
Richard Tan
