Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThe state machine needs to exist in a single process.
You communicate with a process via signals. You can just have outputs from the state machines when something have finished etc, or just read the state of the state machine. It sounds like you're taking VHDL as a programming language. You may need to draw out your intended circuit BEFORE writing any VHDL. without knowing what circuit you want, you will not write the correct VHDL.