Altera_Forum
Honored Contributor
10 years ago"Cant place node <name> -- illegal location assignment INCONSISTENCY"
The fitter produces the error below, which I have no clue how to analyze.
Error (171016): Can't place node "pio2:u0|pio2_hps_0:hps_0|pio2_hps_0_hps_io:hps_io|pio2_hps_0_hps_io_border:border|emac1_inst" -- illegal location assignment INCONSISTENCY File: .../synthesis/submodules/pio2_hps_0_hps_io_border.sv Line: 123
Info (11798): Fitter preparation operations ending: elapsed time is 00:00:00
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Error (11802): Can't fit design in device
I've created a simple 2 GPIO Qsys design reading switches and driving leds on a DE1-SoC board, using a .qsf generated with DE1-SoC System builder. The error also appears when switching devices, i.e. with ALL location assignments removed. Also I tried DE1-SOC.qsf downloaded from the TerASIC website. Actually, I managed to generate a bitfile once, and now the flow is broken again. Any suggestions? BTW I'm using Quartus 15.0