Can't fit 1032 registers in device

Your code is inferring a RAM that will be implemented internally to the MAX device. The MAX device does not contain any RAM so the memory will be constructed from Registers.

The MAX 7128 device contains 128 Registers. The large RAM you are inferring will use 256x4 (1024) registers...which is way too many! The smaller one you tested with will use 5 x 4 (20) registers which easily fits.

Did you intend for the RAM to be an external memory component, i.e not internal to the PLD?

I do not quite understand the connection to the 16 DIP switches. Perhaps you could provide a few more details as to what it is you are trying to design.

Rgds

Hi,

Thanks for your response.

What I am trying to do is to develope a RAM using addressing, control and data buses:

- 8 bit address bus

- 4 bit data bus

- CS, OE, WR, RM (Chip Select, Ouput Enable, Write Memory, Read Memory).

I have been able to configure the 256x4 RAM on the FLEX10K70RC240. Does this mean that the FLEX device contains all the necessary registers to do so?

Here is the code I am using:

entity Memory is

port(

clk: in std_logic;

CS: in std_logic;

OE: in std_logic;

WR: in std_logic;

Addr1: in std_logic_vector(7 downto 0);

Data1: inout std_logic_vector(3 downto 0)

);

end Memory;

architecture behav of Memory is

type ram256x4 is array (255 downto 0)of std_logic_vector(3 downto 0);

signal matriz: ram256x4;

begin

process(CS, OE, clk)

begin

if (clk'event and clk='1') then

if (CS='1')then

case OE is

when '1' =>

Data1<= matriz(conv_integer(Addr1));

when '0' =>

Data1<= (Data1'range => 'Z');

end case;

end if;

if (WR='1') then

matriz(conv_integer(Addr1))<=Data1;

end if;

end if;

end process;

end behav;

Regarding the 16dip switches that come along with the UP2 Education Board. I was intending to implement them as my input ports (Addr1, Data1, OE,....) (to the MAX) avoiding to use any external wires to my board.

Thx,

siLf