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Altera_Forum's avatar
Altera_Forum
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14 years ago

can't find 'clk' pin using get_pins in timequest timing analyzer

using quartus 11.1 build 216 w/service pack 1. My design uses LPM_ADD_SUB components, with the results output registered (not the pipeline registers in the component). I am trying to do report_path...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for your reply.

I once had the same problem as you. (registers driving no logic)

I solved this by using the synthessis attribute noprune.

signal registerIwantToKeep : std_logic;

attribute keep : boolean;

attribute keep registerIwantToKeep : signal is true;