Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThanks much for the answer. Something that's interesting to me, is lack of specific error message, while the synthesis phase is being failed. I was expecting to see kind of verbose somewhere in the log files.
I also have one more question. You've mentioned the inefficiency of my kernel, since I've unrolled the loop manually instead of placing a simple iterative loop and you've said the pipeline is being shared by multiple threads to keep the pipeline busy in NDRange Kernel. Does this mean: 1) Single-Work items designs should be considered as the first choice while deploying an OpenCL code into FPGA? 2) Does Thread here means a single work-item belong to a work-group? Thanks.