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Altera_Forum
Honored Contributor
Honored ContributorCannot edit the generated PLL Intel FPGA IP v18.0
Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
PPrib
New Contributor
New ContributorOctober, 2018 - This is still a problem in 18.1, although luckily the solution described above works. For the file pll_wizard.lst specifically, I search-and-replaced all occurrences of the string
Altera PLL
with
PLL Intel FPGA IP
Quartus now opens the IP Component appropriately.
Intel: What's up?
