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Altera_Forum
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7 years ago

Cannot edit the generated PLL Intel FPGA IP v18.0

Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
Altera_Forum's avatar
Altera_Forum
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7 years ago

schendel,

It also worked for the TSE. It was a bit different in that it did not have an ALIAS at all for v18.0 so I just added:

<ALIAS>Triple-Speed Ethernet Intel FPGA IP v18.0</ALIAS>

and it now works. The contents of the ALIAS were taken from the first line of the generated .vhd file for the core.

Thanks again.