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Altera_Forum
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7 years ago

Cannot edit the generated PLL Intel FPGA IP v18.0

Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
Altera_Forum's avatar
Altera_Forum
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7 years ago

Thank you schendel.

Changing the alias name of the IP in the .lst file does fix the issue. Thanks for the solution.

I started with "root_wizard.lst" and followed a few of the other paths to the individual IP's .lst files. It looks like Intel has not had anybody go through and scrub the all <IP name>.lst files, yet. Sure would have been easier to just leave everything "Altera" and call PSG something like Intel's Altera Group or just Intel/Altera.