Forum Discussion
Altera_Forum
Honored Contributor
8 years agoCannot edit the generated PLL Intel FPGA IP v18.0
Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
Altera_Forum
Honored Contributor
8 years agoThis may be a bug caused by an incorrect replacement of the Altera name by Intel in the ip library.
Until this is fixed, I could fix this like this: > locate the .lst file of the missing IP in your IntelFGPA program directory, for example for the missing PLL, locate: "pll_wizard.lst" > Change the text: "<ALIAS>Altera PLL v18.0</ALIAS> " (and higher version numbers) to: "<ALIAS>PLL Intel FPGA IP v18.0</ALIAS>" I hope this helps you also for the other IPs. Due to all documentation update notices due to the Altera -> Intel re-branding, it is hard to see the real improvements that are being made...