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Altera_Forum
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8 years ago

Cannot edit the generated PLL Intel FPGA IP v18.0

Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi,

We acknowledge this issue and got a bug entry in the internal bug system. We will get back to you once we hear from our engineering team.