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Altera_Forum
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7 years ago

Cannot edit the generated PLL Intel FPGA IP v18.0

Hi All, I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the Me...
Altera_Forum's avatar
Altera_Forum
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7 years ago

I'm having the same problem with "Triple-Speed Ethernet" core. I used to be able to edit the core in a number of ways including opening the EMAC.vhd file generated by the wizard (attached) or double-clicking on the core in "IP Components" view.

I'm on Windows 7 and using "Quartus 18.0 Standard".

This was a project that worked fine in Rev 17.1. When I opened it, it asked to upgrade IP components. That feature seems broken as well since "Perform Automatic Upgrade" etc were greyed out and the only option available was close.

Without a workaround, this essentially makes 18.0 unusable.

https://www.alteraforum.com/forum/attachment.php?attachmentid=15534