Cannot drive PLL from a altclkctrl block

The ALTCLKCTRL block inclk signal has following restriction:

Clock pins, clock outputs from the PLL, and core signals can drive the inclk[] port.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf#page=51, Table 14

The input clock of the ALTCLKCTRL should be driven by a dedicated clock input pin and not just any IO pin.

Regards