Forum Discussion
A_Meerbann
New Contributor
New ContributorCannot drive PLL from a altclkctrl block
I am working on a MAX10 10M50 device with Quartus Prime lite 2021.1.0
My design uses an external IO pin as a clock source. This pin is NOT a dedicatd clock pin.
I instantiated a altclkctrl bock ...
Ash_R_Altera
Regular Contributor
Regular ContributorThe ALTCLKCTRL block inclk signal has following restriction:
Clock pins, clock outputs from the PLL, and core signals can drive the inclk[] port.
Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf#page=51, Table 14
The input clock of the ALTCLKCTRL should be driven by a dedicated clock input pin and not just any IO pin.
Regards
