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A_Meerbann's avatar
A_Meerbann
Icon for New Contributor rankNew Contributor
4 years ago

Cannot drive PLL from a altclkctrl block

I am working on a MAX10 10M50 device with Quartus Prime lite 2021.1.0 My design uses an external IO pin as a clock source. This pin is NOT a dedicatd clock pin. I instantiated a altclkctrl bock ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Can you show your code and how you've made the connections? The warning about CLK[0] not being connected could be part of the issue.