Honored Contributor
Honored ContributorI wonder not know if such jumping is possible.
1. If one programs in assembly language or C, advancing the program counter register to a future value could have unexpected consequences such as corrupting the stack. MS Visual Studio allows mouse dragging the line indicator in C++/VB/C# functions to change back/forth PC location to ease debugging, but under the hood they added lots of auxiliary metadata management to the compiler to enable that. It is not impossible but just difficult. I want to know if Modelsim supports changing the essential "now". Anyway it is a mature (more than two decades) software and the most widely used HDL simulator. I don't know if they have built this into the software. 2. --- Quote Start --- In VHDL (I don't know about Verilog) now holds the current simulation time, I think tcl now is a copy of that. --- Quote End --- I saw you and Tricky in another thread (https://www.alteraforum.com/forum/showthread.php?t=58437&p=237672#post237672) all used VHDL example, and you referred to an limitation of verilog in this one. Does Altera or IC professionals consider verilog incomplete and amateurish, some how like C++ programmers viewing javascript? For example, if we were to write the digital part of some mixed-signal block, say sampling from comparator output, for and ADC, does it feel like that VHDL is better suited, since it is more verbose and gives more direct and strict access to logic elements? greg
