Can we drive QSFP reference clock using an internal clock generated from a PLL

Hi,

As the example design that you are using use this refclk to drive the ATX and fPLL both, their corresponding restrictions apply. For ATX PLL, the restriction is as mentioned in the below document:

https://www.intel.com/content/www/us/en/docs/programmable/683621/current/atx-pll.html

The input reference clock can be driven from one of the following sources. The sources are listed in order of performance, with the first choice giving the highest performance.

• Dedicated reference clock pin
• Reference clock network (with two new high quality reference clock lines)
• Receiver input pin

The input reference clock is a differential signal. Intel® recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.

This explains the error that you are getting.

Regards