Forum Discussion
Altera_Forum
Honored Contributor
8 years ago --- Quote Start --- What about: I - Add a clFlush after each clEnqueueTask() II - Profile the FPGA design (or print all start and end timestamps of the kernels' events) to see if kernels overlap in time. --- Quote End --- I - I thought this was a "no-no" for parallel operations. I'll try it. II - I did "compile" with the profile on the original code (the above it a watered down version of the real objective) and it pretty clearly showed no over lapping.