Forum Discussion
Altera_Forum
Honored Contributor
8 years agoWhat about:
I - Add a clFlush after each clEnqueueTask() II - Profile the FPGA design (or print all start and end timestamps of the kernels' events) to see if kernels overlap in time.What about:
I - Add a clFlush after each clEnqueueTask() II - Profile the FPGA design (or print all start and end timestamps of the kernels' events) to see if kernels overlap in time.