ContributorCan SignalTap ignore periods of inactivity?
Hi. I have some UART code that sends text. My top level module sends a sequence of (English) words to the UART. The UART runs at 9600 Baud which is really slow compared to the FPGA's 50MHz clock.
What I want to do is monitor the state of the top level module but I am not interested in the hundreds (if not thousands) of clock cycles where there are no changes to my top level module's state. I also don't have enough memory on my FPGA to record enough samples between the transmission of individual words. I have the trigger set so that I don't start recording until I move out of my idle state but there are still too many clock cycles to capture. I can't use a sample depth of more than 16k.
Is there anyway in which SignalTap can be configured to ignore these clock cycles of inactivity?
The only other way I can think of diagnosing this problem is to create some sort of pseudo-clock signal that only oscillates a few 50MHz cycles either side of my top module's state transitions. Is that the only way to get around something like this?
