Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

Hi Adzim,

FYI:

The NIOS timing violation are as follows:

Slack from note To Node

-6.263 NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12] NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]
-6.263 NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12] NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]~DUPLICATE
-6.262 NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12] NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[1]
-6.183 NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12] NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]
-6.183 NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12] NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]~DUPLICATE

...

please refer to the attached file for detailed information.

However, even with these timing violation, all functions implemented with NIOS can work well.

Regards,

Scott