Can not edit component in Quartus 7.2 sp1

Hi Leven:

"1. When i adds many verilog files to create a component, SOPC builder automatically choose the top module file for the component and i cant choose another of them for top module."

Yes I've seen this. The first file you add, must contain the top file. Then add the remaining files. I agree this should be fixed.

"2. About the setting for signal of the component, sometimes i can not set my signals as export or clk or reset because the list of "Signal Type" do not contain such types."

They have now added may new types of interfaces to SOPC. Clocks and resets are now under a "Clock Input" type, and Exports are available under the "Conduit Output" and "Conduit Input"

The nice thing, is is you have multiple clocks and resets, you can now define what clock domain what interface is in, and hook it up appropriately in SOPC, with out exporting the extra clocks to the top to figure it out.

Pete