Can I Simulate Each Module in the Project

Hello,

timing simulation can only be performed on gate level netlists and are valid for an individual placed and routed design. In a gate level netlist, the module hierarchy visible at the source level doesn't exist any more.

You have to set a module as top-level entity and recompile the project to perform a ModelSim timing simulation on this module, the same as with Altera simulator. This could be meaningful if the modules internal timing has a significant impact on the designs total timing, or if you want to get typical performance data. But you should be aware, that final designs place and route could change a lot.

Regards,

Frank