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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can i make relative delays in timequest (9.1)

Hi

I am still fairly new to timequest sdc and tcl.

I need to check relative delays instead of absolute delays i a design that does high speed samling of an input pin. (There is no relation between the pin and any clock in the FPGA).

I must check that all delays starting from the same pin has very equal delays to 4 different registers, but the absolute delay are unknown and don't matter.

Also the aboslute delay may change far too must in full corner to make any aboslute check valid. The clocks used are internally generated by PLL's and use reginal clocks to minimize skew between these four clocks.

If it is not possible to check this directly with sdc then I think it should be possible to do it in tcl by reporting all 4 delays to tcl variables and then use tcl to calculate the difference between them and report if the difference is too big. If yo can provide any example of a tcl script doing any thing like that it would be great?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I think you want something like:

    set_max_skew -from [get_ports {sample_port}] 1.0

    Then in your analysis be sure to run report_max_skew(Q10.0 has it run automatically).

    Note that this will take into account on-die variation, which makes the numbers look bad. ODV is the fact that all numbers aren't the same at a corner. For example, at the slow corner, just because some path is analyzed as being worst case, all the other paths might not be quite that bad. This is a true phenomenon and is important for skew. So within a timing model like the slow corner, there are two sub-corners. When it analyzes skew, it will take the slowest path and use the slow-sub model of the Slow Corner, and the other three paths will use the fast sub-model of the slow corner. The clock skews will do the reverse. It tends to make the number look much worse than just doing:

    report_path -from [get_ports {sample_port}] -panel_name "input delays"

    and looking at the difference.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Perfect

    Thanks a lot Rysc this is just what I need. I tryed it in 9.1 TQ gui and it works there.

    The set_max_skew is not shown in the GUI. So therefore I could not find it myself.

    I can find it in help now I know the name. It is part of a sdc extention package, Altera specific I guess, that I did not know about. The fact that is does analyze for subcorners inside the main slow/fast corner is exactly the real world that I need to know about. ( The absolute delay difference between fast and slow corner is about 10 times higher and will never appear in the real world. So I can only dream about one more think?

    Does the fitter use the set_max_skew to minmize the skew ?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    As mentioned, there is a slow and fast sub-model within a corner, which is good, but personally I think it is too high. Specifically the on-die variation would be a lot higher between two pins on opposite side of the die than two pins next to each other, but only having two models, locality and other things can't be taken into account. (I think it errs on being pessimistic, which is good).

    As for the fitter, it can but not in a good way. The placer tries to put all things closer together and wouldn't spread things out. The router is where delays can be added, but it's a pretty coarse tool. My suggestion would be to hand-place the registers into two LABs and see what the router can do from there. If you see a lot of variation, put it into its own hierarchy and make a partition out of it. Do a seed sweep, and lock down the best results with post-fit placement and routing.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi again

    We have allready hand placed the 4 registers close to each other in the second row/colomn from the pin (for some reason the second is better than the first), but we see that the routing variate from fit to fit, the skew might get too big when we have a high fill degree.

    We have never locked down routing and do not know how to do that?

    (Never got around to learn to use the chip planner beside looking at placement, it seems to be quit a job to learn the chip planner GUI.)

    Our general experience is that if you lock down many thinks you can not fit after a small change and it becomes too complex to find out why.

    My first fit after adding a skew of 200pS improved result from around 450ps to max 372pS. I will try with 300ps as 200pS might be too tight.

    Any think else we should set beside optimize multi-corner timing to make it optimize?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    well, i was going to ask if the timing driven place/route would take the set_max_skew and automatically insert delays, but it sounds like the answer is "sort of".

    if i am using the free "web" version of the quartus tools (which does not have LogicLock), am i unable to hand-place logic? i am thinking that i might have to insert delays by hand (either by instantiating buffers or synthesizing inverter chains) and i'd need to hand place that stuff to make sure the delays are controlled.