Occasional Contributor
Frequent ContributorHi Kumar
Are you trying to create a LVDS SERDES function in FPGA or clock generation in FPGA?
Thanks.
Eng Wei
Occasional ContributorYes sir i'am using serializer in transmitter side and deserializer in receiver side.
Frequent ContributorHi Kumar
You can generate example design through IP Catalog following spec here:
Or you can search for relevant functional design example here:
https://fpgacloud.intel.com/devstore/platform/?search=LVDS
Thanks.
Eng Wei
Occasional ContributorThank you, i will update result soon.
Frequent ContributorHi Kumar
Since there is no update on this, we will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
