Forum Discussion
m_kumar
Occasional Contributor
Occasional ContributorCamera Link Transmitter Design
Hi sir/madam. I'm designing an camera link logic to transmit rgb data to through camera link. I stuck with how to generate clock signals for both transmitter side and receiver side. I studied on...
EngWei_O_Intel
Frequent Contributor
Frequent ContributorHi Kumar
Are you trying to create a LVDS SERDES function in FPGA or clock generation in FPGA?
Thanks.
Eng Wei
- m_kumar
Yes sir i'am using serializer in transmitter side and deserializer in receiver side.
- EngWei_O_Intel
Hi Kumar
You can generate example design through IP Catalog following spec here:
Or you can search for relevant functional design example here:
https://fpgacloud.intel.com/devstore/platform/?search=LVDS
Thanks.
Eng Wei
- m_kumar
Thank you, i will update result soon.
