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Honored Contributor
Honored ContributorCall to set_clock_groups fails for Stratix 10 Build
When my SDC file is read while compiling for a Stratix 10 device, the set_clock_groups command is failing. The failure occurs because at the point in time that the SDC file is read, the tool does no...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- what stops you from directly setting clk group to the pll outputs (without using derive pll clocks). You can find the path name from node finder in timequest. --- Quote End --- Nothing. But I would prefer to use the derived names. But If all else fails, that is what I'll do.
