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pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
4 years ago
Solved

Bus index reversal when SystemVerilog module instantiates a BDF in Quartus Prime Pro 21.2

I have a legacy BDF that I need to use in a current design. Using Quartus Prime Pro v20.4 or v21.2, I see the bus indexes reversed on the port connections when the BDF diagram is instantiated from wi...
  • sstrell's avatar
    sstrell
    4 years ago

    Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

Wow, that is really weird! On the off off chance this is SystemVerilog related, can you try a plain .v file instead of .sv?

This is why I don't use schematics anymore!

pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
4 years ago

Thanks. Yeah, I inherited these old schematics and we have been steadily converting the simpler ones to SystemVerilog. The remaining one is big and thoroughly tested, so it hasn't been migrated yet...

I gave your suggestion a try and converted the module to straight Verilog (top.v):

module top
(
    input wire clk,
    input wire [3:0] x,
    output wire [7:0] y
);
wire [7:0] x_in;
assign x_in[7:4] = x;
assign x_in[3:0] = 4'b0;

bdftest bdf_i
(
    .clk(clk),
    .x_in(x_in[7:0]),
    .y_out(y)
);
endmodule

The results were the same:

This is indeed strange!