Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Bus concatenation

Hello all,

I have a 28 bit local bus. I have a RAM with 7 bit address input 6..0. I need to use the schematic editor to make the RAM address input be connected to bits Local_Bus[6..2] and ground the lower two bits of the RAM address input.

To do this I need to concatenate bits from Local_Bus and this Ground bus, which is so very simple in VHDL but after much trying I cannot figure it out in the schematic editor.

Here's a graphic to illustrate the situation. It's sort of a "fill in the blanks." Any ideas are greatly appreciated, thanks! :confused:

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    place a bus on the RAM adress input, name it RAM_addr[6..0].

    place a bus away (without any connection) and name it RAM_addr[6..2]

    place "wire" component (which does nothing in logic) It is like "<=" in VHDL, on input connect Local_bus[6..0], on the ouput connect RAM_addr[6..2]

    ....

    See my schema for ideas.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Or, more simply, connect to the RAM address input a bus named:

    Local_Bus[6..2],Ground[1..0]
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks so much guys, that has really helped me out, and quick. I don't know how I would have done this whole project with out the forums and Altera's quick support responses!