Build a Register

recal in yesterdays question about code and processes, you used the following,

signal cntr_devider : std_logic_vector (23 downto 0);

OK, so once you decalre the signal in the form std_logic_vector you have in fact said it is (in this case) a 24 bit value.

So, for your desired 32 bit binary number you would declare it as (31downto 0).

Note that direction of the vector does matter. (31 downto 0) is flipped from (0 to 31)

With FPGA's it is possible to build a register of almost any size you want.

Hope this helps,

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Thanks for your help

One more question, i need to build a SPI (serial programming interface) for this 32 bit register, do u have any idea how to do this ?

if yes i will be very happy to help me or to write me a code

Thanks

Here are a couple SPI cores from opencores.org

http://www.opencores.org/projects.cgi/web/spi/overview

http://www.opencores.org/projects.cgi/web/simple_spi/overview

Amirster,

The questions you've been asking seem like many I've seen in homework assignments. It's great if you're trying to teach yourself about the technology, but if you're using this forum to do your homework, we're probably doing you a disservice.

Hey :)

I am not doing my homework :)

I am just learning this code for me, and for my knowledge.

I just finish my B.sc in computer science and I am studing VHDL for more knowledge.