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Ivan00's avatar
Ivan00
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4 years ago

Bug report: synthesis optimizes out the signal if data type is declared in generic package

When the data type is declared in the generic package, the synthesis tool removes the signal completely when array slice is used on the right side of the assignment. I have condensed it to the follow...
Ivan00's avatar
Ivan00
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4 years ago

Hi Ean,

is there an update on the issue?

I would really like this VHDL-2008 feature to be supported in the future.

Best regards,

Ivan