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Ivan00
New Contributor
New ContributorBug report: synthesis optimizes out the signal if data type is declared in generic package
When the data type is declared in the generic package, the synthesis tool removes the signal completely when array slice is used on the right side of the assignment. I have condensed it to the follow...
YEan
Contributor
ContributorHi,
The bus length of o_bug was different with the input i. So, the o_bug was not connected. You may change the bus length of o_bug to (17 downto 0).
The entity will be:
--
entity bug is
generic(
G_MODULE_DISABLED : boolean := false;
G_ID : std_logic_vector(7 downto 0) := X"17"
);
port(
i : in std_logic_vector(17 downto 0);
o_bug : out std_logic_vector(17 downto 0);
o_ok : out std_logic_vector(17 downto 0)
);
end entity;
architecture rtl of bug is
signal sp : test_type_t;
begin
sp.pixel_data(0) <= i;
o_bug <= sp.pixel_data(0);
o_ok <= sp.pixel_data(0);
end rtl;
--
Thank you.
Regards,
Ean
