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DGall10
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6 years ago

Bug fix for Quartus 13 .0 or 13.0 sp1 that fixes OR gates acting like AND gates and AND gates acting like OR gates

HI, Im using a RioRand and discovered that when I OR 2 signals either in VHDL or schematic they act like an AND gate and ANDing 2 signals acts like an OR gate. IS there a fix for this?