Boolean Algebra To Gates

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I am new to Quartus (9.1 web edition).

I have a boolean algebra equation: Eg. A or B and C.

It is very lengthy. Is there a wait to automatically generate a circuit using only simple gates such as AND, OR, NOT, etc... based on the boolean algebra expression?

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Hardware description languages such as Verilog and VHDL can be used to implement this type of logic directly, eg. in VHDL the logic is simply

D <= A or B and C;

You can also implement the equivalent logic via

process(A, B, C)
begin
   D <= '0'; -- default value
   if (A = '1') then
     D <= '1';
   elsif (B = '1') then 
     if (C = '1') then
       D <= '1';
     end if;
   end if;
end process;

and the synthesis tool will reduce the complexity to that of the above single line statement (or something equivalent to it).

The second coding style is more verbose, but it generally makes for more readable code, eg., when A, B, and C are finite-state-machine (FSM) inputs, and D is an output (or one of many outputs).

Cheers,

Dave

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AND_test is
port(
	x: in std_logic;
	y: in std_logic;
	F: out std_logic
);
end AND_test;  
architecture behav1 of AND_test is
begin
    F <= x and y;
end behav1;

I have tried using VHDL, and then convert it to a symbol file so I can see it in the bdf diagram.

However, it shows up as a single big block. Is there anyway to convert it so I can see all of the respective And/Or gates in the BDF viewer?

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I have tried using VHDL, and then convert it to a symbol file so I can see it in the bdf diagram.

However, it shows up as a single big block. Is there anyway to convert it so I can see all of the respective And/Or gates in the BDF viewer?

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You want to use the RTL Viewer.

In the Quartus GUI after you've placed-and-routed the design, select Tools->Netlist Viewers->RTL Viewer

Cheers,

Dave