Boarddesign for EP3C25 with DDR2-SDRAM interface with possible migration to EP3C40

Hello everybody,

we are just creating a new design with EP3C25F324 wich should be connected via bank 7 & 8 to DDR2-SDRAM.

Furthermore should it be possible to migrate to EP3C40F324.

Now we are facing some problems in how to configure some I/O-VREF-pins properly without doing any change in board layout.

In detail:

- DDR2 interface requires SSTL-1.8 logic level for I/O's

- in Bank8 for instance is on EP3C25F324 only Pin C7 VRef-pin

- EP3C40F324 has additional VRef pins on location E9, D7, E6

- creating board layout for the two devices in migration path would lead to connecting the 0.9V VRef voltage to all 4 pins

- but how do I have to configure these "additional" VRef pins (E9, D7, E6), which are on EP3C25F324 "ordinary" I/O-pins, to prevent the device from any damage?

- leaving them in the configuration unconnected/unused/unconfigured can't be a solution, even with the default configuration "Reserved Input with weak pull up resistor" which wouldn't have any effect since the pins would be still driven by 0.9V Vref voltage of the migration device.

- is in this case a configuration parameter for this pin available

or

- do we have to modify the board layout?

Best regards (from Berlin/Germany),

det