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Altera_Forum
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9 years ago

Block Diagram File with Parameters - Generate VHDL File not possible (for Simulation)

Hello, please tell me if i got something wrong in my workflow: 1. My Top-Level File is a BDF (Block Diagram File) 2. I placed VHDL Blocks including Generics which are seen as parameters in ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Probably not a bug - just weaknesses in BDF.

Easiest option is probably just write in VHDL in the first place.