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Emirp's avatar
Emirp
Icon for New Contributor rankNew Contributor
3 years ago

Block Diagram - Verilog File Does NOT Run in Block Diagram

Hi, I am an engineering student running the Quartus Prime Lite edition for a digital clock assignment. I'm having some questions about different types of design files. One of the components is writte...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
3 years ago

Without seeing the code for your design and indicating what is correct behavior and what is incorrect behavior, it's hard to figure out what's going on here.