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Emirp's avatar
Emirp
Icon for New Contributor rankNew Contributor
3 years ago

Block Diagram - Verilog File Does NOT Run in Block Diagram

Hi, I am an engineering student running the Quartus Prime Lite edition for a digital clock assignment. I'm having some questions about different types of design files. One of the components is writte...
VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


Do you mind to attach the project.qar file for us to look into your design?

Besides, it is recommended to design the project using Verilog HDL or VHDL instead of BDF and run simulation in Questa or Modelsim instead of running simulation in VWF. Because there is a bug in running simulation in VWF, sometimes it does not work.


Thanks.

Best Regards,

Ven Ting