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Honored Contributor
Honored ContributorBit widths for addition
Hi, I am trying to write a pipelined adder for a filter design. all the gaussianPixels are 8 bits wide. gaussianPartialSum0 <= ("00" & gaussianPixels(0)) + ('0' & gaussianPixels(3) & '0') ...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- In VHDL, the width of the result is as wide as the largest vector in the sum. So 4bits + 2 bits + 2 bits + 1bit = 4 bit result. If you need more, just add more bits to the largest operand --- Quote End --- So in my case those would be the operands to the '+' operator? So in this case, can i just append another zero to the MSB of the gaussianPixel signals so that they are seen by the '+' operator as wider signals? so instead of adding (2+8) + (1+8+1) + (2+8) can I make it (3+8) + (2+8+1) + (3+8) to get the 11 bits i need?
