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Altera_Forum
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11 years ago

Bit widths for addition

Hi, I am trying to write a pipelined adder for a filter design. all the gaussianPixels are 8 bits wide. gaussianPartialSum0 <= ("00" & gaussianPixels(0)) + ('0' & gaussianPixels(3) & '0') ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

In VHDL, the width of the result is as wide as the largest vector in the sum.

So 4bits + 2 bits + 2 bits + 1bit = 4 bit result.

If you need more, just add more bits to the largest operand