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That's a big variance, but I guess it is what it is.
For your set_output_delay, that looks correct except for the sign of the hold, which was already mentioned.
For the set_input_delay, you didn't say but I'm guessing you're sending the clock to the other device and then getting data back? If so, you don't care about the setup and hold of the external device. It's really just the max and min roundtrip delay. So something like:
set_output_delay -max [expr $max_clk_FPGA2Extdev + $Tco_max_Extdev + $max_data_delay_Extdev2FPGA]...
set_output_delay -min [expr $min_clk_FPGA2Extdev + $Tco_min_Extdev + $min_data_delay_Extdev2FPGA]
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Hi Rysc, sorry for the long delay in responding, I've been out of town for a while.
Okay, so if the FPGA is supplying the clock to a device, then setup and hold times on that device can be ignored. That can simplify things.
I have a couple questions regarding signals to devices that don't have clocks:
I have some output enable and directional controls to buffers. The enables turn on once the FPGA is configured and stay on, and the few directionals that do toggle, don't do so rapidly. Is there a value to constraining these signals in the sdc? If so, what would I take into account to determine their min and max?
There are a few interrupt signals that come into the FPGA from off board (we have a code based DMA controller within), they are edge activated and can happen at anytime. Is the trace length delay the only thing that should be taken into consideration for these signals' input delays?
Finally, I have a asynchronous serial interface that communicates with another unit. One singal is transmit, the other is receive. The interface has a constant idle pattern that is transmitted, but data/commands occur at anytime. It's NRZ, so a transition = 1, no transition = 0. The FPGA generates a single ended signal at 60MHz for this and it connects to a PECL converter. This differential signal travels along a cable of varying length (depends on the unit our board is placed in) to reach its destination. To receive, the differential enters our board, gets converted to single ended, and is latched into the FPGA with a 240MHz clock, to ensure all edges are observed correctly. I would assume just using trace length to the PECL converters is where I'd start with these two signals.
Thank you very much for all your help!
Oh, I am looking at taking the online courses from Altera for Timing Analysis; do you feel these are good investments?
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