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Altera_Forum's avatar
Altera_Forum
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11 years ago

Bidirectional IO timing constraints

Hi all, I've created some output delays for a bidirectional data bus, but I wanted to make sure I was getting the input delays set right as well. max board delay = 6.04 min board delay = 1.34...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

That's a big variance, but I guess it is what it is.

For your set_output_delay, that looks correct except for the sign of the hold, which was already mentioned.

For the set_input_delay, you didn't say but I'm guessing you're sending the clock to the other device and then getting data back? If so, you don't care about the setup and hold of the external device. It's really just the max and min roundtrip delay. So something like:

set_output_delay -max [expr $max_clk_FPGA2Extdev + $Tco_max_Extdev + $max_data_delay_Extdev2FPGA]...

set_output_delay -min [expr $min_clk_FPGA2Extdev + $Tco_min_Extdev + $min_data_delay_Extdev2FPGA]