Bidirectional IO timing constraints

Hi Rysc, sorry for the lack of info; let me see if I can clear some of this up.

The wide difference in the min and max board delays are due to the CPU_IO_DATA bus , and the CPU_O_CLK40, passing through 5V tolerant buffers and their way to this CPU. I believe with these buffers it has a minimum 1ns delay, maximum ~5.7ns. I added those values in with the calculated board trace delays. That is also the reason for the clock delays having such a wide variance.

The CPU_O_CLK40 (40MHz clock) is produced inside the FPGA and supplied to the CPU. I got the setup and hold times from its datasheet.

Of course, I can't find my reference for the input delay formula I used. But as I recall, for max it was: max board delay + setup + max clock delay. For min, min board delay + setup + min clock delay.

I really appreciate your help on this!