Bidirectional IO timing constraints

No.

Your constraining a single pin, bit 31, and the max and min board delays are 6.04ns and 1.34ns. I don't know how they could vary that much across different pins unless there's huge board skew, but a single bit couldn't possibly vary that much.

For setup and hold, I assume those are specs of the device it's talking to. Hold is inverted to become a delay, so a hold of 6ns becomes a set_output_delay -min -6. (By say the external delay is -6, then the FPGA must hold the data +6ns to get the delay back to the 0ns hold requirement)

I'm not sure what math you did to get the input delays. Also not sure what your topology is, i.e. is there a board clock driving the FPGA and the external chip, or is the FPGA sending a clock to the external chip or vice versa. I don't know what the clock delays even represent.