Behavioral vs Dataflow/RTL

It can be - components dont have to map to VHDL - they could be verilog code or netlists. A component just defines the interface to some other block. If the other block is VHDL, then components are not needed as you can do direct instantiation.

As for behavioural or data flow - I think all the code you see that is synthesisable in VHDL is behavioural modelling. Dataflow modelling would not map to an FPGA and is often what you can use in testbenches.