Behavior of the safe state machine option

And the safe state machine option for Quartus II synthesis is documented in Altera docs: http://www.altera.com/literature/hb/qts/qts_qii51008.pdf. Other EDA tools gives the same behavior for this type of option I believe.

Safe State Machines

The Safe State Machine option and corresponding syn_encoding

attribute value safe specify that the software should insert extra logic to

detect an illegal state and force the state machine’s transition to the reset

state.

...

It is important to note that the safe state machine value does not use any

user-defined default logic from your HDL code that corresponds to

unreachable states. Verilog HDL and VHDL allow you to explicitly

specify a behavior for all states in the state machine, including

unreachable states. However, synthesis tools detect if state machine logic

is unreachable and minimize or remove the logic. Any flag signals or logic

used in the design to indicate such an illegal state are also removed. If the

state machine is implemented as safe, the recovery logic forces its

transition from an illegal state to the reset state.

...

Safe state machine implementation can result in a noticeable area increase

for the design...