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Do you mean, that there is some subsets of Verilog language - for example one subset (name it Synthesizable) is devoted to hardware synthesis, another subset (name it Behavior) is for modeling ?
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Yes, Only a subset of the verilog language is synthesizable. The higher level functions like $display and $monitor were really meant as aids to debugging the code
Usually you have a top level testbench that is not synthesizable that you that you tell quartus it is not the TOP of your design.
If you have have non-synthesizable debug $displays in your synthesizable code, you tell quartus to ignore these with pragma's //synthesis translate_off and //synthesis translate_on
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For example ModelSim (Mentor Graphics) could compile the upper code.
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Yes. All the simulators will support the non-synthesizable constructs $display, $montitor, etc.
Pete
Honored Contributor
