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As far as I know, those two things aren't synthesizable anywhere, and are purely abstractions used in simulation. Verilog is hardware, and there is no display on your hardware until you build it, and there is no sense of time until you've built it
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Do you mean, that there is some subsets of Verilog language - for example one subset (name it Synthesizable) is devoted to hardware synthesis, another subset (name it Behavior) is for modeling ?
I've been reading the book - "The Verilog Hardware Description Language", Fifth Edition
Donald E. Thomas, Philip R. Moorby. And the code with $monitor and delay instructions is from that book. It suggests an idea to me, that I simply do not understand how to use QuartusII as modeling tool. I don't mean (a Modeling with waveform files), I mean $monitor and delay instruction and so on.
For example ModelSim (Mentor Graphics) could compile the upper code.
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