[beginner] Using design symmetries ?

You can use bottom-up incremental compilation. See the incremental compilation chapter in the Quartus handbook for details.

You would compile the replicated block once, export the compilation results for that block, and import into the Quartus project containing the multiple instantiations of that block. This will work well for synthesis. This will also work to preserve placement (but not routing) if you can place all the instances such that the relative placement within each instance is identical. This requires that the sequence of RAM block, DSP block, and LAB columns overlapped by the replicated circuit be identical for all instances.

For other ways to reduce compilation time, see "Tools --> Advisors --> Compilation Time Advisor". There is an optimization chapter in the Quartus handbook that might have more suggestions than this Advisor covers.