Honored Contributor
Honored ContributorIts not always the fitter's fault. It may be being torn in two directions to meet timing, and ends up giving up. I cant see the ram usage, but if the usage is fairly high, it can start to struggle getting signals in and out of RAMs and DSPs. There are several things to have a play with:
1. Are the rams under heavy utilisation? Its often best to add an extra pipeline stage just to make life easier for the fitter to route into and out of the rams and DSP. Like i said, if it's struggling to meet timing in more than one place, it can sometimes get into a situation where you'll get the same failure coming over and over again because of this routing problem. 2. Try a set_max_delay constraint between the two problem registers , but you may then get a failure in the previous path (so your only option is the extra pipeline register) 3. Have you tried a different fit seed (this only applies if the source code and contraints remain identical). Or even try the design space explorer to try several seeds at the same time (requires multiple licences or a long wait).
