Altera_ForumHonored Contributor14 years agoBad code, but no error, will settle for warning :) This code compiles(!). always @ (posedge clock ) begin state <= NextState; state <= state; state <= 0; end Using the SignalTap it appears that state gets set t...Show More
Recent DiscussionsTiming analysis - long combinational pathQuartusPro 25.3 Crashed after using the Signal Tap Logic AnalyzerDuplicate_hierarchy_depth / duplicate_registerAutomatically added negative node for TDS output doesn't work with Agilex 5Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG